Standards setting organization for the semiconductor electronics industry, such as the JEDEC Solid State Technology Association (formerly the Joint Electron Device Engineering Council and hereinafter referred to as “JEDEC” for convenience), have established standards, such as test methods and product standards, including package standards and interface standards, that are widely employed in the industry.
Among other standards, JEDEC has standardized package dimensions (length×width×height) for Wide I/O and high bandwidth memory (HBM) technologies. The package construction comprises an encapsulated three-dimensional stack of DRAM semiconductor dice (for example, four, eight, twelve or sixteen dice) having conductive vias in the form of so-called “through silicon vias,” or “TSVs,” interconnected using a three-dimensional interconnect architecture using electrically conductive elements in communication with the TSVs extending between adjacent dice and having electrically conductive pillars protruding from a base semiconductor die of the stack to connect to higher level packaging such as a printed circuit board. FIG. 1 schematically depicts a die stack 100 of four DRAM semiconductor dice 102, which structure may also be characterized as a “cube” herein for the sake of convenience. Semiconductor dice 102 of a cube 100 may include TSVs 104, conductive elements 106 in the form of pillars in contact with TSVs 104 (with the exception of top die 102) extending between adjacent dice 102 to landing pads 108 of adjacent dice 102. A dielectric underfill material 110, and a molded encapsulant 112 surround the three upper dice 102 in the cube 100 and abut a major surface of the lowermost die 102. Conductive elements 106 in the form of pillars protrude from the lowermost die 102 for connection to, for example, a logic die or to higher level packaging.
One specific implementation of the stacked die technology, described in the Hybrid Memory Cube Consortium's HMC Specifications 1.0 and 1.1, is the so-called Hybrid Memory Cube (HMC), which places a logic die under a stack of four or eight TSV-bonded DRAM semiconductor dice to form a package ready for connection to, for example, a motherboard bearing a microprocessor, without the need for a separate organic or silicon interposer. With such an approach, memory density and speed may be significantly increased while simultaneously dramatically decreasing power requirements.
While there are several known processes for fabricating assemblies and packaging as described above, a significant challenge to widespread adoption of this technology is testing throughput. In other words, manufacturers must have the capability of shipping massive quantities of “known good cubes” to customers.
To date, the ability to test stacked die assemblies in the form of cubes to qualify them as “known good cubes” has been limited to laborious, single cube testing. There is a need for an automated solution for simultaneous testing of a number of stacked die assemblies.